/*Yipeng Huang and Scott Rogowski*/
/*yh2315 smr2167*/

//The module that handles the write, read, and search for each individual 32 bit word (also can be called a line). 
module Line (write_enable, write_data, read_value, read_valid, clk, reset, start_waiting, is_waiting);

	//standard
	input clk;
	input reset;

	//Write enable and what to write
	input write_enable;
	input [31:0] write_data;
	
	//Read what is currently in the bit and whether the line has been written to before
	output [31:0] read_value;
	output read_valid;

	//For hazards, if we need to wait for this line to be written to again, assert waiting.
	//This controls whether or not program counter continues asking for next instruction.
	input start_waiting;
	output is_waiting;

	//Just to make the compiler be quiet
	wire set;
	assign set = 1'b1;

	//The SR flipflop stores whether this line has been written to before or not.  If it has, the read should be valid
	FF writtenTo (.clk(clk), .enable(write_enable), .set(set), .reset(reset), .q(read_valid)); 
	
	//To implement stalls, aka bubbles, this register should know whether it is waiting to be written back to and NO instructions requiring this register should be allowed to pass through the pipeline until this gets resolved.  Upon being written to, deassert.
	FF waitingOnWriteback (.clk(clk), .enable(start_waiting | write_enable), .set(start_waiting), .reset(reset), .q(is_waiting));
	
	/////////////////Connect the read write functionality across the flip flops //////////////////
	FF my_ff [31:0] (	.clk(clk), .reset(reset),
						.enable(write_enable), .set(write_data[31:0]), .q(read_value[31:0]) );

	endmodule
